1. Field of the Invention
The present invention relates to a vertical MOS transistor having a trench structure and a method of manufacturing the same.
2. Description of the Related Art
FIG. 2 illustrates a schematic sectional view of a conventional vertical MOS transistor having a trench structure. A semiconductor substrate is prepared in which a lightly doped layer 2 of a first conductive (or conductivity) type is epitaxially grown on a heavily doped substrate 1 of the first conductive type to be a drain region. Then, a diffusion region 3 of a second conductive type referred to as a body region is formed from a surface of the semiconductor substrate by impurity implantation and high temperature thermal treatment at 1000xc2x0 C. or higher. Further, from the surface, a heavily doped impurity region 7 of the first conductive type to be a source region and a heavily doped body contact region 8 of the second conductive type for the purpose of fixing a potential of the body region by an ohmic contact are formed and are connected to a source electrode 7a and a body electrode 8a, respectively. Here, since a potential of the source region of the first conductive type and a potential of the body contact region of the second conductive type are usually the same, they are laid out so as to be in contact with each other in FIG. 2. The source electrode 7a and the body electrode 8a are connected with each other through a contact hole, not shown in the figure, for electrically contacting the two regions. Then, a trench 4 is formed by etching single crystalline silicon through the source region of the first conductive type. A gate insulating film 5 and polycrystalline silicon 6 containing a high concentration of impurity to be connected to a gate electrode 9a fill the silicon trench. The heavily doped region of the first conductive type on a rear side of the semiconductor substrate is connected to a drain electrode 1a. 
The above structure can function as a vertical MOS transistor in which current from a drain formed of the heavily doped region of the first conductive type on the rear side and an epitaxial region of the first conductive type to a source formed of the heavily doped region of the first conductive type on a front side is controlled through the gate insulating film on a side wall of the trench by a gate buried in the trench. This method can accommodate both an N channel type and a P channel type by appropriately making the conductive types N or P.
Further, the vertical MOS transistor having the trench structure has a characteristic that, since a channel is formed completely vertically, the transistor allows application of a method for a finer transistor.
A basic structure of such a vertical MOS transistor and a method of manufacturing the same are schematically disclosed in, for example, U.S. Pat. No. 4,767,722, etc.
However, such a structure of a vertical MOS transistor and a method of manufacturing the same have the following problems.
First, in the vertical MOS transistor manufactured by the conventional method, as illustrated in FIG. 2, an upper portion of the polycrystalline silicon filling the trench is concave. Such a concave portion is formed in a process of removing by etching back the polycrystalline silicon film deposited in the trench and on the semiconductor substrate until the surface is planarized. The concave portion is formed because, while the polycrystalline silicon film is deposited as illustrated in FIG. 10 and grains grow vertically on the gate insulating film in the trench, a border between grains formed when the grains come in contact with one another at a center line 11-11xe2x80x2 in the trench has a higher etching rate than that in other regions of the polycrystalline silicon.
When the etching back of the polycrystalline silicon film is carried out excessively, even polycrystalline silicon in contact through the gate insulating film with the body region where the channel in the trench is formed may be removed, which may result in blockage of an operation of the transistor or result in formation of a void when a film is deposited thereon in a later process. Especially when the transistor is operated at a high temperature, a crack may be generated from the void to break the transistor itself. Thus, there is a problem that the etching back of the polycrystalline silicon film has to be carried out under sufficient control.
Secondly, since a gate electrode of the vertical MOS transistor having the trench structure is formed of polycrystalline silicon, there is a problem that a gate resistance is high and such a tendency grows especially as the transistor becomes finer. This impairs the high frequency characteristics. Generally, when the transistor is operated at a frequency of 500 kHz or higher, a delay in switching and lowered efficiency become nonnegligible.
In order to solve the above problems, according to the present invention, a vertical MOS transistor is characterized by a semiconductor substrate of a first conductive type, an epitaxial growth layer of the first conductive type formed on the semiconductor substrate, a body region of a second conductive type formed on the epitaxial growth layer, a trench formed through the body region of the second conductive type so as to reach an inside of the epitaxial growth layer of the first conductive type, a gate insulating film formed along a surface of the body region and a wall surface and a bottom surface of the trench, a polycrystalline silicon gate formed in the trench so as to be in contact with the gate insulating film and surrounded by the gate insulating film, a metal silicide gate as a film formed in the trench so as to be in contact with the polycrystalline silicon gate and surrounded by the gate insulating film and the polycrystalline silicon gate, a source region of the first conductive type formed on the surface of the body region and around the trench so as to be in contact with the gate insulating film, a gate electrode connected to the polycrystalline silicon gate and the metal silicide gate, a source electrode connected to the source region, and a drain electrode connected to the semiconductor substrate.
According to another aspect of the present invention, the vertical MOS transistor is characterized in that a film other than a metal suicide is formed in the trench so as to be in contact with the polycrystalline silicon gate and surrounded by the gate insulating film and the polycrystalline silicon gate, the other film being formed of a silicon compound.
According to still another aspect of the present invention, the vertical MOS transistor is characterized in that the film formed in the trench so as to be in contact with the polycrystalline silicon gate and surrounded by the gate insulating film and the polycrystalline silicon gate is especially a silicon oxide film.
According to yet another aspect of the present invention, the vertical MOS transistor is characterized in that the film formed in the trench so as to be in contact with the polycrystalline silicon gate and surrounded by the gate insulating film and the polycrystalline silicon gate is especially a silicon nitride film.
According to still another aspect of the present invention, the vertical MOS transistor is characterized in that the film formed in the trench so as to be in contact with the polycrystalline silicon gate and surrounded by the gate insulating film and the polycrystalline silicon gate is especially a metal film.
In order to attain the above, a method of manufacturing a vertical MOS transistor is characterized by comprising the steps of forming a body region of a second conductive type from a main surface of a semiconductor substrate of a first conductive type by injection and thermal diffusion of impurity of the second conductive type, forming a trench by carrying out anisotropic etching from a region on the body region where a trench is to be formed through the body region of the second conductive type to an inside of the semiconductor substrate, forming a gate insulating film along a surface of the body region and a wall surface of the trench, depositing on the gate insulating film a polycrystalline silicon layer having a thickness of half or less of the width of the trench, forming on the polycrystalline silicon layer a metal silicide layer as a film having a thickness of more than the difference between half of the trench width and the thickness of the polycrystalline silicon layer, etching the metal silicide layer, etching the polycrystalline silicon layer to form a gate in the trench, and forming a source region of the first conductive type on the surface of the body region and in contact with the gate insulating film.
According to another aspect of the present invention, the method of manufacturing a vertical MOS transistor is characterized in that a film other than a metal silicide is formed on the polycrystalline silicon layer, such as a silicon oxide film.
According to still another aspect of the present invention, the method of manufacturing a vertical MOS transistor is characterized in that the film formed on the polycrystalline silicon layer is a silicon nitride film.
According to yet another aspect of the present invention, the method of manufacturing a vertical MOS transistor is characterized in that the film formed on the polycrystalline silicon layer is a metal film.